april 2011 dsc-2967/15 1 ?2011 integrated device technology, inc. features high-speed address/chip select access time ? military: 20/25/35/45/55/70/85/100ns (max.) ? industrial: 20/25ns (max.) ? commercial: 20/25ns (max.) low power consumption battery backup operation ? 2v data retention voltage (l version only) produced with advanced cmos high-performance technology inputs and outputs directly ttl-compatible three-state outputs available in 28-pin dip, cerdip and soj military product compliant to mil-std-883, class b description the idt7164 is a 65,536 bit high-speed static ram organized as 8k x 8. it is fabricated using idt?s high-performance, high-reliability cmos technology. address access times as fast as 20ns are available and the circuit offers a reduced power standby mode. when cs 1 goes high or cs 2 goes low, the circuit will automatically go to, and remain in, a low-power stand by mode. the low-power (l) version also offers a battery backup data retention capability at power supply levels as low as 2v. all inputs and outputs of the idt7164 are ttl-compatible and operation is from a single 5v supply, simplifying system designs. fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. the idt7164 is packaged in a 28-pin 300 mil dip and soj and a 28- pin 600 mil cerdip. military grade product is manufactured in compliance with the latest revision of mil-std-883, class b, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. functional block diagram address decoder 65,536 bit memory array i/o control 2967 drw 01 we cs v cc gnd i/o 0 i/o 7 control logic oe 2 cs 1 a 0 a 12 0 7 idt7164s idt7164l cmos static ram 64k (8k x 8-bit)
2 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and industrial temperature ranges pin configurations pin descriptions absolute maximum ratings (1) dip/soj top view truth table (1,2,3) recommended operating temperature and supply voltage recommended dc operating conditions 2967 drw 02 5 6 7 8 9 10 11 12 a 12 1 2 3 4 24 23 22 21 20 19 18 17 d28-1 d28-3 p28-2 so28-5 13 14 28 27 26 25 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 v cc we a 8 a 9 a 11 oe a 10 cs 1 i/o 7 16 15 i/o 2 gnd i/o 6 i/o 5 i/o 4 i/o 3 nc cs 2 , name description a 0 - a 12 address i/o 0 - i/o 7 data input/output cs 1 chip select cs 2 chip select we write enable oe output enable gnd ground v cc power 2967 tbl 01 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v cc + 0.5v. symbol rating com'l. mil. unit v te rm (2) te rm i n a l vo l ta g e with respect to gnd -0.5 to +7.0 -0.5 to +7.0 v t a operating temperature 0 to +70 -55 to +125 o c t bias temperature under bias -55 to +125 -65 to +135 o c t stg storage temperature -55 to +125 -65 to +150 o c p t power dissipation 1.0 1.0 w i out dc output current 50 50 ma 2967 tbl 02 notes: 1. cs 2 will power-down cs 1 , but cs 1 will not power-down cs 2 . 2. h = v ih , l = v il , x = don't care. 3. v lc = 0.2v, v hc = v cc - 0.2v we cs 1 cs 2 oe i/o function x h x x high-z deselected - standby (i sb ) x x l x high-z deselected - standby (i sb ) x v hc v hc or v lc x high-z deselected - standby (i sb1 ) xxv lc x high-z deselected - standby (i sb1 ) h l h h high-z output disabled hl h ldata out read data ll hxdata in write data 29 67 tbl 03 grade temperature gnd vcc military -55 o c to +125 o c0v 5v 10% industrial -40 o c to +85 o c0v 5v 10% commercial 0 o c to +70 o c0v 5v 10% 2967 tbl 04 note: 1. v il (min.) = ?1.5v for pulse width less than 10ns, once per cycle. symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ v cc + 0.5 v v il input low voltage -0.5 (1) ____ 0.8 v 2967 tbl 05
6.42 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and i ndustrial temperature ranges 3 dc electrical characteristics (1) (v cc = 5.0v 10%, v lc = 0.2v, v hc = v cc - 0.2v) capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is determined by device characterization, but is not production tested. symbol parameter (1) conditions max. unit c in input capacitance v in = 0v 8 pf c i/o i/o capacitance v out = 0v 8 pf 2967 tbl 06 l o b m y sr e t e m a r a pr e w o p 0 2 s 4 6 1 7 0 2 l 4 6 1 7 5 2 s 4 6 1 7 5 2 l 4 6 1 7 t i n u . l ' m o c. d n i. l i m. l ' m o c. d n i . l i m i 1 c c t n e r r u c y l p p u s r e w o p g n i t a r e p o s c 1 v = l i s c , 2 v = h i n e p o s t u p t u o , v c c f , . x a m = = 0 ) 2 ( s0 0 10 1 10 1 10 90 1 10 1 1 a m l0 90 0 10 0 10 90 0 10 0 1 i 2 c c t n e r r u c g n i t a r e p o c i m a n y d s c 1 v = l i s c , 2 v = h i n e p o s t u p t u o , v c c f = f , . x a m = x a m ) 2 ( s0 7 10 7 10 8 10 7 10 7 10 8 1 a m l0 5 10 5 10 6 10 5 10 5 10 6 1 i b s t n e r r u c y l p p u s r e w o p y b d n a t s , ) l e v e l l t t ( s c 1 > v h i s c , 2 < v l i , v , n e p o s t u p t u o c c f = f , . x a m = x a m ) 2 ( s0 20 20 20 20 20 2 a m l 335335 i 1 b s t n e r r u c y l p p u s r e w o p y b d n a t s l l u f 0 = f , ) l e v e l s o m c ( ) 2 ( v , c c . x a m = . 1 s c 1 > v c h s c d n a 2 > v c h r o , s c . 2 2 < v c l s5 15 10 25 15 10 2 a m l2 . 02 . 012 . 02 . 01 7 0 l b t 7 6 9 2 notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc (all address inputs are cycling at f max ); f = 0 means no address input lines are changing. l o b m y sr e t e m a r a pr e w o p 5 3 s 4 6 1 7 5 3 l 4 6 1 7 5 4 s 4 6 1 7 5 4 l 4 6 1 7 5 5 s 4 6 1 7 5 5 l 4 6 1 7 0 7 s 4 6 1 7 0 7 l 4 6 1 7 0 0 1 / 5 8 s 4 6 1 7 0 0 1 / 5 8 l 4 6 1 7 t i n u . l i m . l i m. l i m. l i m. l i m i 1 c c t n e r r u c y l p p u s r e w o p g n i t a r e p o s c 1 v = l i s c , 2 v = h i n e p o s t u p t u o , v c c f , . x a m = = 0 ) 2 ( s0 0 10 0 10 0 10 0 10 0 1 a m l0 90 90 90 90 9 i 2 c c t n e r r u c g n i t a r e p o c i m a n y d s c 1 v = l i s c , 2 v = h i n e p o s t u p t u o , v c c f = f , . x a m = x a m ) 2 ( s0 6 10 6 10 6 10 6 10 6 1 a m l0 4 10 3 15 2 10 2 10 2 1 i b s t n e r r u c y l p p u s r e w o p y b d n a t s , ) l e v e l l t t ( s c 1 > v h i s c , 2 < v l i , v , n e p o s t u p t u o c c f = f , . x a m = x a m ) 2 ( s0 20 20 20 20 2 a m l5555 5 i 1 b s t n e r r u c y l p p u s r e w o p y b d n a t s l l u f 0 = f , ) l e v e l s o m c ( ) 2 ( v , c c . x a m = . 1 s c 1 > v c h s c d n a 2 > v c h r o , s c . 2 2 < v c l s0 20 20 20 20 2 a m l1111 1 8 0 l b t 7 6 9 2
4 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and industrial temperature ranges dc electrical characteristics (v cc = 5.0v 10%) ac test conditions *includes scope and jig capacitances figure 2. ac test load (for t clz1, t clz2 , t olz , t chz1, t chz2 , t ohz , t ow , and t whz ) figure 1. ac test load data retention characteristics over all temperature ranges (l version only) (v lc = 0.2v, v hc = v cc - 0.2v) 2967 drw 03 480 30pf* 255 data out 5v , 2967 drw 04 480 5pf* 255 data out 5v , symbol parameter test conditions idt7164s idt7164l unit min. max. min. max. |i li | input leakage current v cc = max., v in = gnd to v cc mil. com'l. & ind ____ ____ 10 5 ____ ____ 5 2a |i lo | output leakage current v cc = max., cs 1 = v ih , v out = gnd to v cc mil. com'l. & ind ____ ____ 10 5 ____ ____ 5 2a v ol output low voltage i ol = 8ma, v cc = min. ____ 0.4 ____ 0.4 v i ol = 10ma, v cc = min. ____ 0.5 ____ 0.5 v oh output high voltage i oh = -4ma, v cc = min. 2.4 ____ 2.4 ____ v 2967 tbl 09 notes: 1. t a = +25c. 2. t rc = read cycle time. 3. this parameter is guaranteed by device characterization, but is not production tested. typ. (1) v cc @ max. v cc @ symbol parameter test condition min. 2.0v 3.0v 2.0v 3.0v unit v dr v cc for data retention ____ 2.0 ____ ____ ____ ____ v i ccdr data retention current mil. com'l. & ind ____ ____ 10 10 15 15 200 60 300 90 a t cdr (3 ) chip deselect to data retention time 1. cs 1 > v hc cs 2 > v hc , or 2. cs 2 < v lc 0 ____ ____ ____ ____ ns t r (3) operation recovery time t rc (2) ____ ____ ____ ____ ns i i li i (3) input leakage current ____ ____ ____ 22 a 2967 tbl 10 input pulse levels input rise/fall times input timing reference levels output reference levels ac test load gnd to 3.0v 5ns 1.5v 1.5v see figures 1 and 2 2967 tbl 11
6.42 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and i ndustrial temperature ranges 5 ac electrical characteristics (v cc = 5.0v 10%, all temperature ranges) notes: 1. both chip selects must be active for the device to be selected. 2. this parameter is guaranteed by device characterization, but is not production tested. l o b m y sr e t e m a r a p 0 2 s 4 6 1 7 0 2 l 4 6 1 7 5 2 s 4 6 1 7 5 2 l 4 6 1 7 t i n u . n i m. x a m. n i m. x a m e l c y c d a e r t c r e m i t e l c y c d a e r0 2 _ _ _ _ 5 2 _ _ _ _ s n t a a e m i t s s e c c a s s e r d d a _ _ _ _ 9 1 _ _ _ _ 5 2s n t 1 s c a ) 1 ( e m i t s s e c c a 1 - t c e l e s p i h c _ _ _ _ 0 2 _ _ _ _ 5 2s n t 2 s c a ) 1 ( e m i t s s e c c a 2 - t c e l e s p i h c _ _ _ _ 5 2 _ _ _ _ 0 3s n t 2 , 1 z l c ) 2 ( z - w o l n i t u p t u o o t 2 , 1 - t c e l e s p i h c5 _ _ _ _ 5 _ _ _ _ s n t e o d i l a v t u p t u o o t e l b a n e t u p t u o _ _ _ _ 8 _ _ _ _ 2 1s n t z l o ) 2 ( z - w o l n i t u p t u o o t e l b a n e t u p t u o0 _ _ _ _ 0 _ _ _ _ s n t 2 , 1 z h c ) 2 ( z - h g i h n i t u p t u o o t 2 , 1 - t c e l e s p i h c _ _ _ _ 9 _ _ _ _ 3 1s n t z h o ) 2 ( z - h g i h n i t u p t u o o t e l b a s i d t u p t u o _ _ _ _ 8 _ _ _ _ 0 1s n t h o e g n a h c s s e r d d a m o r f d l o h t u p t u o5 _ _ _ _ 5 _ _ _ _ s n t u p ) 2 ( e m i t p u r e w o p o t t c e l e s p i h c0 _ _ _ _ 0 _ _ _ _ s n t d p ) 2 ( e m i t n w o d r e w o p o t t c e l e s e d p i h c _ _ _ _ 0 2 _ _ _ _ 5 2s n e l c y c e t i r w t c w e m i t e l c y c e t i r w0 2 _ _ _ _ 5 2 _ _ _ _ s n t 2 , 1 w c e t i r w - f o - d n e o t t c e l e s p i h c5 1 _ _ _ _ 8 1 _ _ _ _ s n t w a e t i r w - f o - d n e o t d i l a v s s e r d d a5 1 _ _ _ _ 8 1 _ _ _ _ s n t s a e m i t p u - t e s s s e r d d a0 _ _ _ _ 0 _ _ _ _ s n t p w h t d i w e s l u p e t i r w5 1 _ _ _ _ 1 2 _ _ _ _ s n t 1 r w ( e m i t y r e v o c e r e t i r w s c 1 , e w )0 _ _ _ _ 0 _ _ _ _ s n t 2 r w s c ( e m i t y r e v o c e r e t i r w 2 )5 _ _ _ _ 5 _ _ _ _ s n t z h w ) 2 ( z - h g i h n i t u p t u o o t e l b a n e e t i r w _ _ _ _ 8 _ _ _ _ 0 1s n t w d p a l r e v o e m i t e t i r w o t a t a d0 1 _ _ _ _ 3 1 _ _ _ _ s n t 1 h d e m i t e t i r w m o r f d l o h a t a d( s c 1 , e w )0 _ _ _ _ 0 _ _ _ _ s n t 2 h d s c ( e m i t e t i r w m o r f d l o h a t a d 2 )5 _ _ _ _ 5 _ _ _ _ s n t w o ) 2 ( e t i r w - f o - d n e m o r f e v i t c a t u p t u o4 _ _ _ _ 4 _ _ _ _ s n 2 1 l b t 7 6 9 2
6 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and industrial temperature ranges ac electrical characteristics (con't.) (v cc = 5.0v 10%, military temperature ranges) notes: 1. both chip selects must be active for the device to be selected. 2. this parameter is guaranteed by device characterization, but is not production tested. l o b m y sr e t e m a r a p 5 3 s 4 6 1 7 5 3 l 4 6 1 7 5 4 s 4 6 1 7 5 4 l 4 6 1 7 5 5 s 4 6 1 7 5 5 l 4 6 1 7 0 7 s 4 6 1 7 0 7 l 4 6 1 7 0 0 1 / 5 8 s 4 6 1 7 0 0 1 / 5 8 l 4 6 1 7 t i n u . x a m. n i m. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m e l c y c d a e r t c r e m i t e l c y c d a e r5 3 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 5 8 _ _ _ _ s n t a a e m i t s s e c c a s s e r d d a _ _ _ _ 5 3 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 5 8s n t 1 s c a ) 1 ( e m i t s s e c c a 1 - t c e l e s p i h c _ _ _ _ 5 3 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 5 8s n t 2 s c a ) 1 ( e m i t s s e c c a 2 - t c e l e s p i h c _ _ _ _ 0 4 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 5 8s n t 2 , 1 z l c ) 2 ( z - w o l n i t u p t u o o t 2 , 1 - t c e l e s p i h c5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t e o d i l a v t u p t u o o t e l b a n e t u p t u o _ _ _ _ 8 1 _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 5 3 _ _ _ _ 0 4s n t z l o ) 2 ( z - w o l n i t u p t u o o t e l b a n e t u p t u o0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t 2 , 1 z h c ) 2 ( z - h g i h n i t u p t u o o t 2 , 1 - t c e l e s p i h c _ _ _ _ 5 1 _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 5 3s n t z h o ) 2 ( z - h g i h n i t u p t u o o t e l b a s i d t u p t u o _ _ _ _ 5 1 _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 5 3s n t h o e g n a h c s s e r d d a m o r f d l o h t u p t u o5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t u p ) 2 ( e m i t p u r e w o p o t t c e l e s p i h c0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t d p ) 2 ( e m i t n w o d r e w o p o t t c e l e s e d p i h c _ _ _ _ 5 3 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 5 8s n e l c y c e t i r w t c w e m i t e l c y c e t i r w5 3 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 5 8 _ _ _ _ s n t 2 , 1 w c e t i r w - f o - d n e o t t c e l e s p i h c5 2 _ _ _ _ 3 3 _ _ _ _ 0 5 _ _ _ _ 0 6 _ _ _ _ 5 7 _ _ _ _ s n t w a e t i r w - f o - d n e o t d i l a v s s e r d d a5 2 _ _ _ _ 3 3 _ _ _ _ 0 5 _ _ _ _ 0 6 _ _ _ _ 5 7 _ _ _ _ s n t s a e m i t p u - t e s s s e r d d a0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t p w h t d i w e s l u p e t i r w5 2 _ _ _ _ 5 2 _ _ _ _ 0 5 _ _ _ _ 0 6 _ _ _ _ 5 7 _ _ _ _ s n t 1 r w ( e m i t y r e v o c e r e t i r w s c 1 , e w )0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t 2 r w s c ( e m i t y r e v o c e r e t i r w 2 )5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t z h w ) 2 ( z - h g i h n i t u p t u o o t e l b a n e e t i r w _ _ _ _ 4 1 _ _ _ _ 8 1 _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 5 3s n t w d p a l r e v o e m i t e t i r w o t a t a d5 1 _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 5 3 _ _ _ _ s n t 1 h d e m i t e t i r w m o r f d l o h a t a d( s c 1 , e w )0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t 2 h d s c ( e m i t e t i r w m o r f d l o h a t a d 2 )5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t w o ) 2 ( e t i r w - f o - d n e m o r f e v i t c a t u p t u o4 _ _ _ _ 4 _ _ _ _ 4 _ _ _ _ 4 _ _ _ _ 4 _ _ _ _ s n 3 1 l b t 7 6 9 2
6.42 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and i ndustrial temperature ranges 7 timing waveform of read cycle no. 1 (1) notes: 1. we is high for read cycle. 2. device is continuously selected, cs 1 is low , cs 2 is high. 3. address valid prior to or coincident with cs 1 transition low and cs 2 transition high. 4. oe is low. 5. transition is measured 200mv from steady state. timing waveform of read cycle no. 2 (1,2,4) timing waveform of read cycle no. 3 (1,3,4) address cs 1 oe data out cs 2 t rc t aa t oh t acs2 t clz2 (5) t oe t acs1 t clz1 (5) t olz (5) t chz2 (5) t ohz (5) t chz1 (5) data valid 2967 drw 05 2967 drw 06 address data out t rc t aa t oh t oh data valid data out t acs2 (5) cs 1 cs 2 t clz2 t acs1 (5) t clz1 t pu t pd i cc i sb t chz2 (5) t chz1 (5) data valid power supply current 2967 drw 07
8 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and industrial temperature ranges timing waveform of write cycle no. 1 ( we controlled timing) (1,5) timing waveform of write cycle no. 2 ( cs controlled timing) (1) notes: 1. a write occurs during the overlap of a low we , a low cs 1 and a high cs 2 . 2. t wr1, 2 is measured from the earlier of cs 1 or we going high or cs 2 going low to the end of the write cycle. 3. during this period, i/o pins are in the output state so that the input signals must not be applied. 4. if the cs 1 low transition or cs 2 high transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. oe is continuously high. if oe is low during a we controlled write cycle, the write pulse width must be the larger of t wp or (t whz +t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse width is as short as the specified t wp . 6. transition is measured 200mv from steady state. address t wc t whz (6) 2967 drw 08 cs 1 data out cs 2 t as t aw t wr1 (2) we t wp t ow (6) data in t dh1,2 t dw data valid (3) (5) address cs 1 cs 2 t wc t as we t cw t wr2 (2) t aw data in t dh1,2 t dw data valid t wr1 (2) (4) 2967 drw 09
6.42 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and i ndustrial temperature ranges 9 ordering information low v cc data retention waveform 2967 drw 10 data retention mode 4.5v 4.5v v dr 2v v ih v ih t r t cdr v cc cs v dr x power xx speed xxx package x process/ temperature range blank i b commercial (0 c to +70 c) industrial (-40 c to +85 c) military (-55c to +125c) compliant with mil-std-883, class b y tp d td 300 mil soj (so28-5) 300 mil plastic dip (p28-2) 600 mil cerdip (d28-1) 300 mil cerdip (d28-3) s l standard power low power device type 7164 2967 drw 11 x g green blank 8 tube or tray tape and reel x 20 25 35 45 55 70 85 100 commercial/industrial/military military only
10 idt7164s/l cmos static ram 64k (8k x 8-bit) military, commercial, and industrial temperature ranges datasheet document history 01/13/00 updated to new format pp. 1, 2, 3, 5, 10 added industrial temperature range offerings pp. 1, 3, 9 removed commercial 70ns speed grade offering pp. 1, 3, 6, 10 added 100ns speed grade specification details pg. 3 revised notes and footnotes in dc electrical tables pp. 5, 6 revised notes and footnotes in ac electrical tables pg. 8 removed note 1 from write cycle no. 1 and no. 2 diagrams; renumbered notes and footnotes pp. 9, 10 separated ordering information into commercial, industrial, and military offerings pg. 11 added datasheet document history 08/09/00 not recommended for new designs 02/01/01 removed "not recommended for new designs" 12/07/01 pg. 10 add pj28 to industrial temperature. 09/30/04 pg. 9,10 added "restricted hazardous substance device" to ordering information. 11/16/06 pg.3 added inustrial temp power limits for 20ns part. changed power limits for 25ns part for commercial and industrial. changed power limits for commercial and industrial for 35ns part. pg.10 added 20ns part to ordering information. refer to pcn sr-0602-01 02/20/07 pg. 9, 10 added l generation die step to data sheet ordering informatiom. 04/27/11 pg. 1-3,5,6,9 obsoleted 24-pin 600 mil, 15ns for commercial and 35ns for industrial & commercial. added tape and reel to ordering information and updated description of restricted hazardous substance device to green. the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or ipchelp@idt.com san jose, ca 95138 408-284-8200 800-345-7015 fax: 408-284-2775 www.idt.com
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